1. Field of the Invention
The present invention relates to a burn-in test method for use in a semiconductor memory device, and more particularly to a circuit and method for performing the burn-in test.
2. Background of the Related Art
Semiconductor devices are liable to process defects and other problems. The ratio of defects also increases in proportion to the integration density of the semiconductor chip.
It is also well known, as the integration density of semiconductor chips increase, the size of each of the transistors contained within becomes smaller.
Therefore, if the applied external D.C. power voltage is applied to the transistor of reduced size without correspondingly lowering the applied D.C. power voltage, effects of the electrical field are increased, thereby causing more defects in the transistor.
In order to ensure the reliability of memory chips, it is well known in the art to perform a burn-in test after the chip is fabricated to detect defective memory cells. The burn-in test applies a voltage exceeding the external power voltage to the gate of memory cell transistors at a high temperature for a long time in order to detect defective memory cells within the chip. This excessive stress helps to easily detect the defects.
A conventional burn-in test method will now be described in detail with reference to a memory chip. In known dynamic RAMs (Random Access Memory), only a given word line can be set to logic "high" during one row address strobe RAS cycle. Thus, a plurality of rows are sequentially enabled to logic "high". FIG. 1 illustrates the overall chip architecture of a 4 Meg DRAM. The memory cell array of the illustrated 4 Meg DRAM is arranged in a matrix of four subarrays each having 1024 rows. The 1024 rows of each subarray are sequentially enabled to logic "high" from a first row. Specifically, if one row address strobe signal RAS is applied with an active signal, respective first rows of memory cell arrays 1M, 1M', 1M" and 1M"' are set to logic "high", and if the row address strobe signal RAS is applied with a precharge signal, respective first rows of the memory cell arrays 1M, 1M', 1M" and 1M"' are reset. Thereafter, if the row address strobe signal RAS is again applied with the active signal, respective second rows of the memory cell arrays 1M, 1M', 1M" and 1M"' are set to logic "high". This process is repeated for all 1024 rows and by so doing, all the cell arrays are sequentially set to logic "high", to perform the burn-in test.
If a burn-in time of 72 hours (this time is variable according to the characteristics of the chip) is selected, the stress of the high voltage is applied to each access transistor for about 4.2 minutes total.
However, as the number of memory cells in the chip increase, the above-described burn-in test method requires increasing the total burn-in time. In a 16 Meg DRAM, for instance, in order to give the stress time of 4.2 minutes per access transistor, a burn-in time of 288 hours (72.times.4) is needed, and in the case of a 64 Meg DRAM, a burn-in time of 576 hours (72.times.8) is required. Consequently, it takes a long time to complete a burn in test of a single memory chip. Moreover, with this known technique, it is still difficult to consider burn-in test effective because 4.2 minutes of burn-in time is not enough to ensure the reliability for a complete burn-in test. However, in order to increase this time in any significant manner, the overall test time must increase substantially.